Developments in networks-on-chip (NOCs) in the last decade have demonstrated great promise in handling several of the key challenges facing digital system designers in the deep submicron era, including design time, scalability, reliability and ease-of-integration. However, recent findings still predict significant challenges and short-comings in terms of system latency, throughput and power consumption.
One approach that has been explored to address such challenges is elimination of the global clock, either using entirely asynchronous systems or integrating synchronous cores, nodes and memories through asynchronous communication in a globally-asynchronous locally synchronous (GALS) system. GALS systems offer the potential of more flexible integration of heterogeneous components, such as heterochronous systems that have arbitrary unrelated clock domains.
A number of recent approaches have also been explored for dynamic adaptivity in both synchronous and asynchronous domains. These approaches include asynchronous dynamic leakage management and synchronization reduction in multi-synchronous NOCs as well as other synchronous approaches, including express virtual channels.